Centre cuts silicon fab support to 40% under Semicon 2.0

India’s Semiconductor Push Enters Phase Two With Tighter Fab Subsidies and Broader Ecosystem Coverage

Indiadailyupdate.com – New Delhi has recalibrated its flagship semiconductor incentive programme, trimming the headline subsidy for silicon fabrication plants while simultaneously widening the net of government support to encompass display manufacturing, advanced packaging, equipment production, and early-stage chip design. The revised framework, formally notified on Monday, marks the operational launch of Semicon 2.0 — a scheme carrying a total outlay of ₹1.27 lakh crore that received Union Cabinet approval in July.

The most visible change concerns the core silicon fab incentive. Under the original 2022 programme, commonly referred to as Semicon 1.0, qualifying fabrication facilities could claim up to 50 percent of their total project cost as central-government assistance. The successor scheme now caps that figure at 40 percent, applied on an equivalent basis to eligible capital expenditure. In practical terms, a fab spending ₹10,000 crore on construction and tooling would see its maximum central subsidy drop from ₹5,000 crore to ₹4,000 crore.

Ministerial Rationale: Confidence Has Replaced Skepticism

Union Minister for Electronics and Information Technology Ashwini Vaishnaw addressed reporters on Monday to explain the recalibration. His central argument was that the Indian semiconductor ecosystem has matured to the point where a lower subsidy rate no longer deters investment. He cited accelerating industry momentum, improving ease of doing business, and what he described as India’s growing policy certainty as factors that shaped the government’s calculus.

“When we started Semicon 1.0 in 2022, the global semicon majors had serious doubts about India. That doubt is now replaced by confidence. They now believe India is the right place for making major investments in the coming decades,” said Vaishnaw.

He characterised the revised support level as “globally competitive” — deliberately positioned neither at the extreme low end nor the extreme high end of international subsidy benchmarks. The implicit message to multinational chipmakers already evaluating Indian sites: the policy environment itself, not the subsidy percentage, has become the primary draw.

Architecture of the Revised Scheme

Semicon 2.0 is organised around six thematic pillars and ten distinct categories of financial support. The pillars span the full value chain: chip design, machines and materials, expanded semiconductor fabs, advanced packaging, research and development, and talent development. This architecture represents a deliberate shift from the narrower, fab-centric focus of its predecessor toward a whole-ecosystem approach.

The ₹1.27 lakh crore envelope is distributed across these categories, with each pillar receiving its own allocation and eligibility criteria. The scheme’s breadth is intended to reduce India’s dependence on imported equipment, materials, and packaging services — sectors where the country currently imports the overwhelming majority of inputs.

Display Fabs Enter the Framework

A notable new addition is dedicated support for display fabrication facilities. The scheme now covers three display technologies: OLED, Micro LED, and LCD. The financial thresholds and subsidy rates differ by technology:

OLED and LCD display projects must commit a minimum investment of ₹10,000 crore to qualify, and eligible projects receive 35 percent central support. Micro LED projects face a lower entry threshold of ₹1,500 crore but receive the same 35 percent subsidy rate. This tiered structure acknowledges the vastly different capital intensity of large-area OLED/LCD lines compared with emerging Micro LED production.

Advanced Packaging and Legacy Packaging

Packaging — the process of encapsulating and interconnecting finished dies into usable modules — has been carved out as a distinct support category. Advanced packaging techniques, including 2.5D and 3D stacking, wafer-level chip-scale packaging, and heterogeneous integration, qualify for 35 percent support. Older, legacy packaging projects receive a lower rate of 25 percent, creating an incentive gradient that nudges investment toward next-generation interconnect and stacking methodologies.

Equipment, Materials, and Domestic Sourcing Incentives

The revised scheme extends eligibility to manufacturers of semiconductor equipment, sub-assemblies, and components, as well as producers of wafers, photomasks, photoresists, substrates, specialty chemicals, process gases, and other semiconductor-grade materials. This is a direct attempt to build a domestic supply chain for the inputs that fabs consume daily.

Equipment makers additionally qualify for a separate production-linked incentive calibrated to the value of components they source from Indian manufacturers. The mechanism rewards vertical integration within the country rather than rewarding mere assembly of imported parts.

Chip Design: Seed Capital and Equity Co-Investment

For the commercial chip-design segment, the scheme introduces differentiated support by company size. Startups and micro, small, and medium enterprises (MSMEs) can access seed funding of up to ₹15 crore, alongside equity co-investment from the government. Larger eligible design houses may tap royalty financing or equity co-investment structures, aligning government returns with the commercial success of the funded IP.

What the Recalibration Signals

The reduction in the silicon fab subsidy, set against the expansion into packaging, display, equipment, and design, suggests a policy maturation. India’s first-generation semiconductor push (2022–2025) was largely about attracting anchor fab investments — the headline-grabbing, multi-billion-dollar fabrication plants. The second generation appears designed to thicken the surrounding ecosystem: the suppliers, the packaging partners, the design houses, and the talent pipeline that make a fab operation sustainable beyond the initial construction phase.

For industry stakeholders already operating under Semicon 1.0 commitments, the transition mechanics and grandfathering provisions will determine whether in-progress projects retain the earlier 50 percent rate or migrate to the new 40 percent ceiling. The scheme’s notification documents, now publicly available, outline the eligibility windows and application timelines for each of the ten support categories.